DRAMs are widely used for temporary storage of large amounts of data, thanks to the simplicity and compactness of the memory cells. A DRAM memory cell consists in fact of a selection transistor and a charge-storage capacitor, in which the information is stored in form of an electric charge. The selection transistor allows accessing the storage capacitor for either writing the information therein or reading the stored information.
Compared to SRAMs, which have memory cells formed by four or even six transistors, DRAMs occupies substantially less semiconductor area and are therefore cheaper devices.
A problem of DRAMs, not encountered in SRAMs, is the need of periodically refreshing the information stored in the memory cells. Unavoidable leakages in the storage capacitors cause a decrease in time of the charge stored therein and, eventually, the loss of the information.
Refreshing the information involves reading the information stored in each memory cell and then rewriting the same information, thereby restoring the prescribed electric charge in the storage capacitors. The external device, for example the microprocessor controlling the DRAM needs to access twice every single memory location, firstly for reading the data stored therein and then for rewriting the read data. This operation increases significantly the workload of the microprocessor.
DRAMs have been proposed capable of autonomously carrying out the refresh of the memory cells, thus relieving the microprocessor of this burden.
One such DRAM is disclosed in U.S. Pat. No. 5,999,474. The memory comprises several banks of DRAM cells and a control circuit for accessing and refreshing the DRAM cells. The DRAM banks can operate-independently of each other, so that parallel operations such as read, write and refresh can take place in different DRAM banks simultaneously. An SRAM cache is incorporated in the DRAM, for storing the recently accessed data. When access is requested to the recently accessed data present in the SRAM cache, the latter is accessed instead of the DRAM banks, so that the refresh operation can go on in the DRAM banks.
The SRAM cache has the same storage capacity and organization as a DRAM bank, and is configured as a direct map cache: a one-to-one positioning correspondence exists between the SRAM cache locations and the memory locations in the DRAM banks.
A limitation of the direct-mapping scheme is that two steps are necessary to access a memory location: in a first step a cache tag is accessed, to determine the DRAM bank associated with the accessed SRAM cache location; in a second step the bank number retrieved from the cache tag is compared to the bank number included in the access address, to ascertain whether the content of the accessed memory location is already present in the SRAM cache or not. This two-step access process increases the memory access time.
Another limitation of the cache direct-mapping scheme is that the cache memory must have at least the same storage capacity as a DRAM bank (same number of memory locations). This has a significant impact in terms of semiconductor chip area. The SRAM cache occupies an area at least approximately four times the area of a DRAM bank: the area occupied by the SRAM cache can be comparable with the overall area occupied by the DRAM banks.
An additional limitation of the cache memory being configured as a direct-map cache, involving a highly inflexible allocation scheme based on a rigid positioning correspondence between the DRAM locations and the cache locations, is the high number of cache misses, especially when sequences of adjacent DRAM locations need to be accessed.
A further limitation of the cache direct-mapping scheme is the inefficient exploitation of the SRAM cache storage capacity. Already allocated cache locations need to be replaced even if the cache is still partially empty. This increases the power consumption of the memory device, especially when a write-back from the SRAM cache into the DRAM banks takes place.